View UPD16448A_5271.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

DATA SHEET
MOS INTEGRATED CIRCUIT
PD16448A
SOURCE DRIVER FOR 240-OUTPUT TFT-LCD (NAVIGATION, AUTOMOBILE LCD-TV)
PD16448A is a source driver for TFT liquid crystal panels. This IC consists of a multiplexer circuit supporting a
variety of pixel arrays, a shift register that generates sampling timing, and two sample and hold circuits that sample analog voltages. Because the two sample and hold circuits alternately execute sampling and holding, a high definition can be obtained. In addition, simultaneous sampling and successive sampling are automatically selected according to the pixel array of the LCD panel. It is ideal for a wide range of applications, including navigation systems and automobile LCDTVs.
FEATURES
* Can be driven on 5 V (Dynamic range: 4.3 V, VDD2 = 5.0 V) * 240-output * fmax. = 18 MHz (VDD1 = 3.0 V) * Simultaneous/successive sampling selectable according to pixel array Simultaneous sampling: vertical stripe Successive sampling: * Two sample and hold circuits * Low output deviation between pins ( 20 mV MAX.) * Stripe, delta, and mosaic pixel arrays supported by internal multiplexer circuit * Left and right shift selected by R/L pin * Single-side mounting possible delta array, mosaic array
ORDERING INFORMATION
Part Number
PD16448AN-xxx
Package
TCP (TAB package)
Remark The dimensions of TCP are custom-made. Please consult NEC for details.
The information in this document is subject to change without notice. Document No. S11712EJ3V0DS00 (3rd edition) Date Published August 1998 NS CP(K) Printed in Japan The mark 5 shows major revised points.
(c)
1998
PD16448A
BLOCK DIAGRAM
CLI1 to 3 R/L STHR 240-bit shift register STHL 3
INH 240-bit level shifter RESET
VDD1 +3.3 V VSS1 VSS2 GND
C1 C2 C3 Multiplexer 240-bit sample and hold buffer
VSS3 VDD2
+5.0 V
MP/TH MP/1.5 H1
..................................................................................................... H240
SAMPLE AND HOLD CIRCUIT AND OUTPUT CIRCUIT
VIDEO LINE Swa1 CH1 Hn
- +
Swb1
- +
Swa2 CH2
Swb2
2
PD16448A
5
PIN CONFIGRATION ( PD16448A N-xxx)
C1 C2 C3 VDD2 VDD1 STHL MP/TH MP/1.5 R/L RESET INH CLI1 CLI2 CLI3 TEST STHR VSS1 VSS3 VSS2 Copper Foll suface
H240 H239 H238 H237 * * * * * * * * * * H5 H4 H3 H2 H1
Remark This figure does not spesify the TCP package.
3
PD16448A
1. PIN DESCRIPTION
Symbol C1 to C3 H1 to H240 STHR STHL CLI1 CLI2 CLI3 INH RESET Name Video signal input Video signal output Cascade I/O Input R, G, and B video signals. Video signal output pins. Output sampled and held video signals during horizontal period. Start pulse I/O pins of sample hold timing. STHR serves as an input pin and STHL, as an output pin, in the case of right shift. In the case of left shift, STHL serves as an input pin, and STHR, as an output pin. A start pulse is read at the rising edge of CLI1. Sampling pulse SHPn is generated at the rising edge of CLI1 through CLI3 during successive sampling, and at the rising edge of CLI1 during simultaneous sampling (for details, refer to the Timing charts in 2.FUNCTION DESCRIPTION). Selects a multiplexer and one of the two sample and hold circuits at the falling edge. Resets the select counter of the multiplexer and the selector circuit of the two sample and hold circuits when it goes high. After reset, the multiplexer is turned OFF, so sure to input one pulse of the INH signal before inputting the video signal. If the video signal is input without the INH signal, sampling is not executed. Four types of color filter arrays can be supported by combination of MP/TH and MP/1.5. Mode Vertical stripe array MP/1.5 Multiplexer circuit select input (2) Single-side delta array Mosaic array Double-side delta array MP/TH L L H H MP/1.5 L H L H Function
Shift clock input
Inhibit input Reset input
MP/TH
Multiplexer circuit select input (1)
R/L VDD1 VDD2 VSS1 VSS2 VSS3 TEST
Shift direction select input Logic power supply Driver power supply Logic ground Driver ground Driver ground Test pin
R/L = H; right shift: STHR H1 H240 STHL R/L = L; left shift: STHL H240 H1 STHR 3.0 V to 5.5 V 5.0 V 0.5 V Connect this pin to ground of system. Connect this pin to ground of system. Connect this pin to ground of system. Fix this pin to L.
4
PD16448A
2. FUNCTION DESCRIPTION
2.1 Multiplexer Circuit
This circuit selects RGB video signals input to the C1, C2, and C3 pins according to the pixel array of the liquid crystal panel, and outputs the signals to the H1 through H240 pins. Vertical stripe array, single-/double-side delta array, or mosaic array can be selected by using the MP/TH and MP/1.5 pins. 2.1.1 Vertical stripe array mode (MP/TH = L, MP/1.5 = L) In this mode, the relation between video signals C1, C2, and C3, and output pins is as shown below. This mode is used to drive a panel of vertical stripe array. In this mode, the multiplexer circuit is in the through status. Relation between video signals C1, C2, and C3, and output pins (during right shift)
Line No. (number of INHs) 0 1 2 3 : :
RESET
INH
H1 (H240) Sampling C1 (C3) Output C1 (C3) Output C1 (C3) Output C1 (C3) : :
H2 (H239) Sampling C2 (C2) Output C2 (C2) Output C2 (C2) Output C2 (C2) : :
H3 (H238) Sampling C3 (C1) Output C3 (C1) Output C3 (C1) Output C3 (C1) : :
H4 (H237) Sampling C1 (C3) Output C1 (C3) Output C1 (C3) Output C1 (C3) : :
H239 (H2) Sampling C2 (C2) Output C2 (C2) Output C2 (C2) Output C2 (C2) : :
H240 (H1) Sampling C3 (C1) Output C3 (C1) Output C3 (C1) Output C3 (C1) : :
H L L L : :
L : :
( ) indicates the case of left shift. Pixel arrangement of vertical stripe array and multiplexer operation
R C1 B C2 G C3
PD16448A
Right shift (R/L = "H"), MP/TH = "L", MP/1.5 = "L" H3 H4 H5 H6 H7
H1
H2
R R R R R
B B B B B
G G G G G
R R R R R
B B B B B
G G G G G
R R R R R
5
PD16448A
Timing chart of vertical stripe array
RESET INH H1 (H240) sampling input data Output H2 (H239) sampling input data Output H3 (H238) sampling input data Output
Undefined
C1 (C3)
C1 (C3) C1 (C3)
C1 (C3) C1 (C3)
C1 (C3) C1 (C3)
C1 (C3) C1 (C3) C1 (C3)
Undefined
Undefined
C2 (C2)
C2 (C2) C2 (C2)
C2 (C2) C2 (C2)
C2 (C2) C2 (C2)
C2 (C2) C2 (C2) C2 (C2)
Undefined
Undefined
C3 (C1)
C3 (C1) C3 (C1)
C3 (C1) C3 (C1)
C3 (C1) C3 (C1)
C3 (C1) C3 (C1) C3 (C1)
Undefined
H239 (H2) sampling input data Output H240 (H1) sampling input data Output

Undefined
C2 (C2)
C2 (C2) C2 (C2)
C2 (C2) C2 (C2)
C2 (C2) C2 (C2)
C2 (C2) C2 (C2) C2 (C2)
Undefined
Undefined
C3 (C1)
C3 (C1) C3 (C1)
C3 (C1) C3 (C1)
C3 (C1) C3 (C1)
C3 (C1) C3 (C1) C3 (C1)
Undefined
6
PD16448A
2.1.2 Single-side delta array mode (MP/TH = L, MP/1.5 = H) Relation between video signals C1, C2, and C3, and output pins
Line No. (number of INHs) 0 1 2 3 4 5
RESET
INH
H1 (H240)
H2 (H239)
H3 (H238)
H4 (H237)
H239 (H2)
H240 (H1)
H L L L L L
L
Undefined Sampling C1 (C3) Output C1 (C3) Output C2 (C1) Output C1 (C3) Output C2 (C1)
Undefined Sampling C2 (C2) Output C2 (C2) Output C3 (C3) Output C2 (C2) Output C3 (C3)
Undefined Sampling C3 (C1) Output C3 (C1) Output C1 (C2) Output C3 (C1) Output C1 (C2)
Undefined Sampling C1 (C3) Output C1 (C3) Output C2 (C1) Output C1 (C3) Output C2 (C1)
Undefined Sampling C2 (C2) Output C2 (C2) Output C3 (C3) Output C2 (C2) Output C3 (C3)
Undefined Sampling C3 (C1) Output C3 (C1) Output C1 (C2) Output C3 (C1) Output C1 (C2)
( ) indicates the case of left shift. Pixel arrangement of single-side delta array and multiplexer operation
R C1 B C2 G C3
PD16448A
H1 H2 H3
Right shift (R/L = H), MP/TH = "L", MP/1.5 = "H" H4 H5 H6 H7
R B R B R B R G G G
B R B R B R B
G B G B G B G
R G R G R G R
B R B R B R B
G B G B G B G
R G R G R G R
7
PD16448A
Timing chart of single-side delta array
RESET INH H1 (H240) sampling input data Output H2 (H239) sampling input data Output H3 (H238) sampling input data Output H239 (H2) sampling input data Output H240 (H1) sampling input data Output
Undefined
Undefined
C1 (C3) Undefined
C2 (C1) C1 (C3)
C1 (C3) C2 (C1)
C2 (C1) C1 (C3) C2 (C1)
Undefined
Undefined
C2 (C2) Undefined
C3 (C3) C2 (C2)
C2 (C2) C3 (C3)
C3 (C3) C2 (C2) C3 (C3)
Undefined
Undefined
Undefined
C3 (C1) Undefined
C1 (C2) C3 (C1)
C3 (C1) C1 (C2)
C1 (C2) C3 (C1) C1 (C2)
Undefined
Undefined
Undefined
C2 (C2) Undefined
C3 (C3) C2 (C2)
C2 (C2) C3 (C3)
C3 (C3) C2 (C2) C3 (C3)
Undefined
Undefined
Undefined
C3 (C1) Undefined
C1 (C2) C3 (C1)
C3 (C1) C1 (C2)
C1 (C2) C3 (C1) C1 (C2)
Undefined
8
PD16448A
2.1.3 Double-side delta array mode (MP/TH = H, MP/1.5 = H) Because the pad pitch of the PD16448A is designed so that the IC is mounted on one side, the output pitch must be expanded on the TCP if the IC is mounted on both sides. Relation between video signals C1, C2, and C3, and output pins
Line No. (number of INHs) 0 1 2 3 4 5
RESET
INH
H1 (H240)
H2 (H239)
H3 (H238)
H4 (H237)
H239 (H2)
H240 (H1)
H L L L L L
L
Undefined Sampling C2 (C3) Output C2 (C3) Output C1 (C1) Output C2 (C3) Output C1 (C1)
Undefined Sampling C3 (C2) Output C3 (C2) Output C2 (C3) Output C3 (C2) Output C2 (C3)
Undefined Sampling C1 (C1) Output C1 (C1) Output C3 (C2) Output C1 (C1) Output C3 (C2)
Undefined Sampling C2 (C3) Output C2 (C3) Output C1 (C1) Output C2 (C3) Output C1 (C1)
Undefined Sampling C3 (C2) Output C3 (C2) Output C2 (C3) Output C3 (C2) Output C2 (C3)
Undefined Sampling C1 (C1) Output C1 (C1) Output C3 (C2) Output C1 (C1) Output C3 (C2)
( ) indicates the case of left shift. Pixel arrangement of double-side delta array and multiplexer operation
R C1 B C2 G C3
PD16448A
H1 H2
Right shift (R/L = "H"), MP/TH = "H", MP/1.5 = "H" H3 H3
R B R G
B R B
G B G
R G R
B R B
G B G
R G R
R B G
B R
G B
R G
B R
G B
R G
H240 G C1 R C2 B C3
H239
H238
H237
PD16448A
Left shift (R/L = "L"), MP/TH = "H", MP/1.5 = "H"
9
PD16448A
Timing chart of double-side delta array
RESET INH
H1 (H240) sampling input data Output H2 (H239) sampling input data Output H3 (H238) sampling input data Output

Undefined
Undefined
C2 (C3) Undefined
C1 (C1) C2 (C3)
C2 (C3) C1 (C1)
C1 (C1) C2 (C3) C1 (C1)

Undefined
Undefined
C3 (C2) Undefined
C2 (C3) C3 (C2)
C3 (C2) C2 (C3)
C2 (C3) C3 (C2) C2 (C3)
Undefined
Undefined
Undefined
C1 (C1) Undefined
C3 (C2) C1 (C1)
C1 (C1) C3 (C2)
C3 (C2) C1 (C1) C3 (C2)
Undefined
H239 (H2) sampling input data Output H240 (H1) sampling input data Output

Undefined
Undefined
C3 (C2) Undefined
C2 (C3) C3 (C2)
C3 (C2) C2 (C3)
C2 (C3) C3 (C2) C2 (C3)
Undefined
Undefined
Undefined
C1 (C1) Undefined
C3 (C2) C1 (C1)
C1 (C1) C3 (C2)
C3 (C2) C1 (C1) C3 (C2)
Undefined
10
PD16448A
2.1.4 Mosaic array mode (MP/TH = H, MP/1.5 = L) Relation between video signals C1, C2, and C3, and output pins
Line No. (number of INHs) 0 1 2 3 4 5 : :
RESET
INH
H1 (H240)
H2 (H239)
H3 (H238)
H4 (H237)
H239 (H2)
H240 (H1)
H L L L L L : :
L : :
Undefined Sampling C1 (C3) Output C1 (C3) Output C3 (C2) Output C2 (C1) Output C1 (C3) : :
Undefined Sampling C2 (C2) Output C2 (C2) Output C1 (C1) Output C3 (C3) Output C2 (C2) : :
Undefined Sampling C3 (C1) Output C3 (C1) Output C2 (C3) Output C1 (C2) Output C3 (C1) : :
Undefined Sampling C1 (C3) Output C1 (C3) Output C3 (C2) Output C2 (C1) Output C1 (C3) : :
Undefined Sampling C2 (C2) Output C2 (C2) Output C1 (C1) Output C3 (C3) Output C2 (C2) : :
Undefined Sampling C3 (C1) Output C3 (C1) Output C2 (C3) Output C1 (C2) Output C3 (C1) : :
( ) indicates the case of left shift. Pixel arrangement of mosaic array and multiplexer operation
R C1 G C2 B C3
PD16448A
H1 H2 H3
Right shift (R/L = "H"), MP/TH = "H", MP/1.5 = "L" H4 H5 H6 H7
R B G R B
G R B G R
B G R B G
R B G R B
G R B G R
B G R B G
R B G R B
11
PD16448A
Timing chart of mosaic array
RESET INH
H1 (H240) sampling input data Output H2 (H239) sampling input data Output H3 (H238) sampling input data Output

Undefined
Undefined
C1 (C3) Undefined
C3 (C2) C1 (C3)
C2 (C1) C3 (C2)
C1 (C3) C2 (C1) C1 (C3)

Undefined
Undefined
C2 (C2) Undefined
C1 (C1) C2 (C2)
C3 (C3) C1 (C1)
C2 (C2) C3 (C3) C2 (C2)
Undefined
Undefined
Undefined
C3 (C1) Undefined
C2 (C3) C3 (C1)
C1 (C2) C2 (C3)
C3 (C1) C1 (C2) C3 (C1)
Undefined
H239 (H2) sampling input data Output H240 (H1) sampling input data Output

Undefined
Undefined
C2 (C2) Undefined
C1 (C1) C2 (C2)
C3 (C3) C1 (C1)
C2 (C2) C3 (C3) C2 (C2)
Undefined
Undefined
Undefined
C3 (C1) Undefined
C2 (C3) C3 (C1)
C1 (C2) C2 (C3)
C3 (C1) C1 (C2) C3 (C1)
Undefined
12
PD16448A
2.1.5 Relation between Shift Clock CLIn and Internal Sampling Pulse SHPn (1) Simultaneous sampling (( ) indicates the case of left shift.)
CLI1 STHR (STHL) SHP1 (SHP240) SHP2 (SHP239) SHP3 (SHP238) SHP4 (SHP237) SHP5 (SHP236) SHP6 (SHP235) C1 sampling C2 sampling C3 sampling C1 sampling C2 sampling C3 sampling
Remark C1 through C3 are sampled while SHPn is H. (2) Successive sampling (( ) indicates the case of left shift.)
CLI1 CLI2 CLI3 STHR (STHL) SHP1 (SHP240) SHP2 (SHP239) SHP3 (SHP238) SHP4 (SHP237) SHP5 (SHP236) SHP6 (SHP235) C1 sampling C2 sampling C3 sampling C1 sampling C2 sampling C3 sampling 3-phase clock
Remarks 1. Input a three-phase clock to shift clock pins CLI1 through CLI3. 2. The video signals (C1, C2, and C3) are sampled while SHPn is H.
13
PD16448A
2.2 Sample and Hold Circuit The sample and hold circuit samples and holds the video input signals C1 through C3 selected by the multiplexer circuit in the timing shown below. Swa1 through Swb2 are reset by the RESET signal and change at the rising and falling edges of the INH signal. (Refer to BLOCK DIAGRAM.)
RESET Undefined
Data INH Swa1 Swa2 Swb1 Swb2
Undefined
on
on
14
PD16448A
5 2.3 Write Operation Timing The sampled video signals are written to the LCD panel by output currents IVOL and IVOH via output buffer. The dynamic range is 4.3 VMIN. (VDD2 = 5.0 V). While INH = H, do not stop shift clocks CLI1 through CLI3. The output operation of this IC is controlled by INH signals. INH = Hiz INH = Connected with internal circuit (switch sample and hold circuit at the falling edge.) Therefore, performing Vcom inversion while INH = L causes current flow to these IC output pins, which may result in malfunction. Perform Vcom in version during INH = H (Hi-z) and start output operation of the next line after the Vcom signal is stable enough to operate. Make sure to evaluate this output operation sufficiently.
INH
Output voltage
1 horizontal period
1 horizontal period
Vcom
15
PD16448A
[Cautions on Use] 1. Turn ON power to VDD1, logic input, VDD2, and video signal input in that order to prevent destruction due to latchup, and turn off power in the reverse sequence. Observe this power sequence even during the transition period. 2. This IC is designed to input successive signals such as chrome signals. The input band of the video signals is designed to be 9 MHz not performed correctly. 3. Insert a bypass capacitor of 0.1 F between VDD1 and VSS1 and between VDD2 and VSS2. If the power supply is not reinforced, the sampling voltage may be abnormal if the supply voltage fluctuates. 4. 5. 6. Display may not be correctly performed if noise is superimposed on the start pulse pin. Therefore, be sure to input a reset signal during the vertical blanking period. Even if the start pulse width is extended by half a clock or more, sampling start timing SHP1 is not affected, and the sampling operation is performed normally. When the multiplexer circuit is used in the vertical stripe mode, C1, C2, and C3 are simultaneously sampled at the rising edge of SHPn. Internally, however, only CLI1 is valid. Therefore, input a shift clock to CLI1 only. At this time, keep the CLI2 and CLI3 pins to "L". When using the multiplexer circuit in the delta array mode or mosaic array mode, C1, C2, and C3 are sequentially sampled. Input a three-phase clock to CLI1 through CLI3. (For the sampling timing, refer to 2. FUNCTION DESCRIPTION.) 7. The recommended timing of tR-1 and PWRES on starting is shown below. (The following timing chart shows simultaneous sampling.) An INH pulse width of at least 5 clocks is required to reset the internal logic. Unless the INH pulse is input after reset, sampling is not performed in the correct sequence.
MAX.
If video signals faster than that are input, display is
CLI1 1 PWRES RESET tISETUP tR-I INH 3 clocks MIN. STHR (STHL) tIHOLD PWINH: 5 clocks MIN. 2 3 4 5 1 2 3
SHP1 to 3 SHP4 to 6 SHP7 to 9
16
PD16448A
3.ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS (TA = 25 C, VSS1 = VSS2 = 0 V)
Parameter Logic supply voltage Driver supply voltage Logic input voltage Video input voltage Logic output voltage Driver output voltage Driver output current Operating temperature range Storage temperature range Symbol VDD1 VDD2 VI VVI V01 V02 IO2 TA Tstg C1, C2, C3 Condition Ratings -0.5 to +7.0 -0.5 to +7.0 -0.5 to VDD1 +0.5 -0.5 to VDD2 +0.5 -0.5 to VDD1 +0.5 -0.5 to VDD2 +0.5 10 -30 to +85 -65 to +125 Unit V V V V V V mA C C
Caution If the absolute maximum rating of even one of the above parameters is exceeded eve momentarily, the quality of the product may be degraded. Absolute maximum ratings, therefore, specify the values exceeding which the product may be physically damaged. Be sure to use the product within the range of the absolute maximum ratings.
RECOMMENDED OPERATING CONDITIONS (TA = -30 to +85 C, VSS1 = VSS2 = 0 V)
Parameter Logic supply voltage Driver supply voltage Video input voltage Driver output voltage Input voltage, high Input voltage, low Symbol VDD1 VDD2 VVI V02 VIH VIL MIN. 3.0 4.5 VSS2 + 0.35 VSS2 + 0.35 0.7*VDD1 0 TYP. 3.3 5.0 MAX. 5.5 5.5 VDD2 - 0.35 VDD2 - 0.35 VDD1 0.3*VDD1 Unit V V V V V V
17
PD16448A
ELECTRICAL CHARACTERISTICS (TA = -30 to +85 C, VDD1 = 3.0 to 5.5 V, VDD2 = 5.0 V 0.5 V, VSS1 = VSS2 = 0 V)
Parameter Maximum video signal output voltage Minimum video signal output voltage Logic output voltage, high Logic output voltage, low Video signal output current, high Video signal output current, low Reference voltage 1 Reference voltage 2 Reference voltage 3 Output voltage deviation 1 Output voltage deviation 2 Output voltage deviation 3 Logic input leakage current Video input leakage current Logic dynamic current consumption Symbol VVOH VVOL VLOH VLOL IVOH IVOL VREF1 VREF2 VREF3 VVO1 VVO2 VVO3 ILL IVL IDD1 fCLI = 14 MHz VVI = 2.0 V, no load fINH = 15.4 kHz PWINH = 5.0 s fCLI = 14 MHz VVI = 2.0 V, no load fINH = 15.4 kHz PWINH = 5.0 s VDD1 = 3.3 0.3 V VDD1 = 5.0 0.5 V STHL, STHR pins IOH = -1.0 mA STHL, STHR pins IOL = 1.0 mA INH = L VO = VDD2 - 0.5 V INH = L Vof = 1.0 V, VO = 0.5 V VDD2 = 5.0 V, TA = 25 C VVI = 0.5 V VDD2 = 5.0 V, TA = 25 C VVI = 2.0 V VDD2 = 5.0 V, TA = 25 C VVI = 3.5 V VDD2 = 5.0 V, TA = 25 C VVI = 0.5 V VDD2 = 5.0 V, TA = 25 C VVI = 2.0 V VDD2 = 5.0 V, TA = 25 C VVI = 3.5 V -0.08 -0.20 0.20 0.49 1.99 3.49 20 20 20 1.0 10 2.5 4.0 10.0 mA 0.9*VDD1 0.1*VDD1 -0.08 Condition MIN. VDD2 - 0.35 0.35 TYP. MAX. Unit V V V V mA mA V V V mV mV mV
A A
mA
Driver dynamic current consumption
IDD2
Remarks 1. Vof: output applied voltage, VO: output voltage without load 2. The reference values are typical values only. The output deviation is only guaranteed within the chip.
18
PD16448A
SWITCHING CHARACTERISTICS (TA = -30 to +85 C, VDD1 = 3.0 to 5.5 V, VDD2 = 5.0 0.5 V, VSS1 = VSS2 = 0 V)
Parameter Start pulse propagation delay time Symbol tPHL tPLH Maximum clock frequency 1 Maximum clock frequency 2 Logic input capacitance STHL, STHR input capacitance Video input capacitance fmax. 1 fmax. 2 CI1 CI2 C3 With 3-phase clock input Other than STHL, STHR STHL, STHR C1 to C3, VVI = 2.0 V Condition CL = 20 pF CL = 20 pF MIN. 10 10 15 8 15 20 50 TYP. MAX. 54 54 Unit ns ns MHz MHz pF pF pF
TIMING REQUIREMENTS (TA = -30 to +85 C, VDD1 = 3.0 to 5.5 V, VDD2 = 5.0 0.5 V, VSS1 = VSS2 = 0 V)
Parameter Clock pulse width Start pulse setup time Start pulse hold time Reset pulse width INH setup time INH hold time Reset-INH time INH pulse width Symbol PWCLI tSETUP tHOLD PWRES tISETUP tIHOLD tR-I PWINH Condition Duty = 50 % MIN. 33 8 8 66 33 33 81 5 TYP. MAX. Unit ns ns ns ns ns ns ns CLK
Remark Keep the rise and fall times of the logic input signals to within tr = tf = 5 ns (10 to 90%). As an example, the switching characteristic wave of CLI1 is defined on the next page.
19
PD16448A
SWITCHING CHARACTERISTIC WAVE (simultaneous/successive sampling) Start Pulse Input Timing
PWCLI1
PWCLI1 VDD1
CLI1
50 %
50 % VSS1 tSETUP tHOLD VDD1
STHR (STHL)
50 %
50 % VSS1
VDD1 SHP1 (SHP240) VSS1
Start Pulse Output Timing
VDD1 CLI1 50 % 50 % VSS1
tPLH
tPHL
VOH STHL (STHR) 50 % 50 % VOL
Remark The input/output timing of the start pulse is the same for simultaneous/successive sampling.
20
PD16448A
5 RESET INH Pulse Timing
CLI1
50%
PWRES
RESET
50%
50%
tISETUP
tIIHOLD
INH
50% 50%
tR-I
PWINH
21
PD16448A
4. RECOMMENDED CONDITIONS FOR INSTALLATION
This product should be installed under the following recommended conditions. representatives for installation under conditions other than those recommended.
Installation Condition Thermocompression bonding Installation Method Soldering ACF (sheet type adhesive agent) Condition Heat with heating tool at 300 C to 350 C under pressure of 100 g (per pin) for 2 to 3 seconds Temporary adhesion at 70 C to 100 C under pressure of 3 to 2 8 kg/cm for 3 to 5 seconds Permanent adhesion at 165 C to 180 C under pressure of 25 to 2 45 kg/cm for 30 to 40 seconds (when aeolotropic conductive film SUMIZAC 1003 from Sumitomo Bakelite Co., Ltd. is used)
Consult one of our sales
Caution For installation conditions for the ACF part, contact the ACF manufacturer beforehand. Do not mix different installation methods.
22
PD16448A
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
23
PD16448A
REFERENCE
NEC Semiconductor Device Reliability/Quality Control System Quality Grade on NEC Semiconductor Devices C10983E C11531E
The application circuits and their parameters are for reference only and are not intended for use in actual design-ins.
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product.
M4 96. 5

▲Up To Search▲

Price & Availability of UPD16448A

	To Download UPD16448A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .